The present invention relates in general to fabrication methodologies and resulting structures for semiconductor devices. More specifically, the present invention is related to fabrication methodologies and resulting structures for embedding magnetic tunnel junction (MTJ) pillars into back-end-of-line interconnects, wherein the embedded MTJ pillar has reduced height and uniform contact area.
Integrated circuits (ICs) are fabricated in a series of stages, including a front-end-of-line (FEOL) stage, a middle-of-line (MOL) stage and a back-end-of-line (BEOL) stage. The process flows for fabricating modern ICs are often identified based on whether the process flows fall in the FEOL stage, the MOL stage, or the BEOL stage. Generally, the FEOL stage is where device elements (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate/wafer. The FEOL stage processes include wafer preparation, isolation, gate patterning, and the formation of wells, source/drain (S/D) regions, extension junctions, silicide regions, and liners. The MOL stage typically includes process flows for forming the contacts and other structures that couple to active regions (e.g., gate/source/drain) of the FEOL device elements. Layers of interconnections are formed above these logical and functional layers during the BEOL stage to complete the IC.
Memory structures such as MTJ stacks can be embedded in BEOL interconnect structures. The MTJ stack can be part of an MTJ pillar that includes the MTJ stack, a cap formed on the MTJ stack, and a conductive hardmask formed over the cap. The MTJ pillar can be electrically accessed through a top contact coupled to the conductive hardmask, and a bottom contact coupled to the bottom of the MJT stack.